The electronic industry has demonstrated a great need for small discrete power MOSFETs with low on-resistances (RDSon), large blocking voltages (VDSBR), and low gate charges in addition to adequate ruggedness. Ruggedness defines the safe operating area (SOA) and the unclamped inductive switching (UIS) of the device. With an optimum combination of these characteristics, extremely low on-state power losses and switching losses can be achieved, resulting in high power conversion efficiencies in systems such as DC-DC converters.
Ultra dense trench-gated power MOSFET technology has been developed to meet these needs. By shrinking cell pitch, i.e., reducing the size of the power MOSFET so that more power MOSFETs can be formed per square area of silicon, a lower on-resistance can be achieved. But often this is accompanied by a decrease in device ruggedness. In order to resolve this negative impact, the device having a reduced cell pitch must be designed to absorb more energy (including DC and dynamic power dissipations) before catastrophic failure occurs.
The basic concept of trench-gated power MOSFET technology is illustrated with reference to FIGS. 1-3. FIG. 1 represents a conventional trench-gated power MOSFET 10. A gate 12 is in a trench 14 formed within a P-well 16. With respect to forming the source/body contact regions 18, a corresponding etch mask must be aligned to the trench 14. The dielectric layer 20 between the source electrode 22 and the gate oxide layer 24 overlays a portion of the flat surface of the N+ source region 26. The dimension of the dielectric layer 20 that overlays the N+ source region 26 is determined by the maximum gate-source rating. Therefore, the minimum cell pitch of the conventional structure is limited by the source/body contact masking misalignment tolerance plus the spacing taken by the surface dielectric layer 20.
This limitation is eliminated by using the trench technology illustrated in FIGS. 2 and 3. In the resulting device structure 28, the gate 12 is recessed into the trench 14, leaving a recess region large enough for the dielectric layer 20. The depth of the recess region, which will determine the final thickness of the dielectric layer 20, is determined by the maximum gate-source rating. After the dielectric layer 20 has been deposited, it is etched back using the flat silicon surface 32 as the ending point.
Compared to the conventional trench-gated power MOSFET 10 as shown in FIG. 1, this device 28 provides very high channel densities. The cross sectional views of this device 28 at the different locations labeled 3a and 3b in FIG. 2 are respectively illustrated in FIGS. 3a and 3b. In order to form the device 28 with a very small cell pitch without the stringent requirement of the source/body contact etch mask step, the P+ source/body contact region 18 is interrupted and periodically placed along its N+ stripe, where the N+ source region 26 is completely excluded.
Unfortunately, the periodic placement of the P+ source/body contact region 18 increases the on-resistance of the device 28, as well as the base resistance and the common base current gain of the parasitic BJT. The parasitic BJT is formed by the N+ source region 26, the P-well 16 and the N epitaxial layer 9. As a consequence, the parasitic BJT will be turned on at a very low current, resulting in a poor SOA and a lower UIS capability.